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Flexible static memory controller (FSMC)
RM0008
19.4.1
NOR/PSRAM address mapping
HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 84 .
Table 84.
NOR/PSRAM bank selection
00
01
10
11
HADDR[27:26] (1)
Selected bank
Bank 1 NOR/PSRAM 1
Bank 1 NOR/PSRAM 2
Bank 1 NOR/PSRAM 3
Bank 1 NOR/PSRAM 4
1. HADDR are internal AHB address lines that are translated to external memory.
HADDR[25:0] contain the external memory address. Since HADDR is a byte address
whereas the memory is addressed in words, the address actually issued to the memory
varies according to the memory data width, as shown in the following table.
Table 85.
External memory address
Memory width (1)
8-bit
16-bit
Data address issued to the memory
HADDR[25:0]
HADDR[25:1] >> 1
Maximum memory capacity (bits)
64 Mbytes x 8 = 512 Mbit
64 Mbytes/2 x 16 = 512 Mbit
1. In case of a 16-bit external memory width, the FSMC will internally use HADDR[25:1] to generate the
address for external memory FSMC_A[24:0].
Whatever the external memory width (16-bit or 8-bit), FSMC_A[0] should be connected to external memory
address A[0].
Wrap support for NOR Flash/PSRAM
Each NOR Flash/PSRAM memory bank can be configured to support wrap accesses.
On the memory side, two cases must be considered depending on the access mode:
asynchronous or synchronous.
●
●
Asynchronous mode : in this case, wrap accesses are fully supported as long as the
address is supplied for every single access.
Synchronous mode : in this case, the FSMC issues the address only once, and then
the burst transfer is sequenced by the FSMC clock CLK.
Some NOR memories support linear burst with wrap-around accesses, in which a fixed
number of words is read from consecutive addresses modulo N (N is typically 8 or 16
and can be programmed through the NOR Flash configuration register). In this case, it
is possible to set the memory wrap mode identical to the AHB master wrap mode.
Otherwise, in the case when the memory wrap mode and the AHB master wrap mode
cannot be set identically, wrapping should be disabled (through the appropriate bit in the
FSMC configuration register) and the wrap transaction split into two consecutive linear
transactions.
19.4.2
412/995
NAND/PC Card address mapping
In this case, three banks are available, each of them divided into memory spaces as
indicated in Table 86 .
Doc ID 13902 Rev 9
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